The present invention relates to a printed circuit board noise calculating method and a design support apparatus using a CAD program for a printed circuit board having semiconductor devices and decoupling capacitors constituting an information processing apparatus such as a personal computer, a server, a router and a storage.
Important guide lines for designing a printed circuit board include realizing functions provided by mounted components, reducing power source noises, reducing electromagnetic radiation from an apparatus, and the like. Reducing power source noises are particularly important from the viewpoint of ensuring stable operations of components mounted on a printed circuit board, such as semiconductor devices, analog devices and RF components. It is also important to suppress power source noises because the power source noises may become an exciting source of electromagnetic radiation noises.
A flow chart illustrated in FIG. 2 is generally used as a printed circuit board design method which can suppress electromagnetic radiation noises by optimizing a board layout. Namely, after a startup, board information is input at Step 110, and component arrangement information is input at Step 120. By using these two pieces of the information, an electromagnetic field is analyzed at Step 130 to model the board. This model and a semiconductor device model are connected to analyze noises at circuit analysis Step 150. Power source noises greatly dependent upon board layout so that component arrangement can therefore be estimated at a design stage. It is judged at Step 200 whether the estimated power source noises are larger or smaller than a target value. If noises exceed the target value, the component is rearranged at Step 210. Information after the component is rearranged at Step 210 is processed by a sequence of the electromagnetic field analysis Step 130 and following Step which are repeated until the judgment Step 200 is satisfied.
Component arrangement optimizing techniques are disclosed, for example, in JP-A-2001-147952 and JP-A-2004-362074. According to these techniques, after layout of a printed circuit board, models of a power source system and a ground system are formed through electromagnetic field analysis, and the two-dimensional distribution of voltage and current in the board is displayed to identify excessive noise regions. A capacitor is disposed near the excessive noise region to reduce noises.
JP-A-2000-293560 discloses techniques of speeding up electromagnetic field analysis and circuit analysis. Electromagnetic field analysis (FDTD) and circuit analysis (SPICES) are performed alternately at each step to improve an analysis precision of devices including an IC circuit.
A circuit design method disclosed in JP-A-2004-145410 allows even a person not skilled in an analog circuit to perform an optimum circuit constant design taking a circuit variation into consideration, by using Taguchi methods.
JP-A-10-207926 discloses a design approach using an orthogonal array.